Appeal No. 1999-2681
Application No. 08/656,998
BACKGROUND
The appellants’ invention relates to a knowledge driven simulation time and data
reduction technique. The system compares the simulated values to the desired values to
determine any discrepancy. If the discrepancy is greater than a predetermined amount,
the simulation is stopped thereby saving time. An understanding of the invention can be
derived from a reading of exemplary claim 1, which is reproduced below.
1. A simulator for simulating a digital circuit, comprising:
an input circuit for inputting a plurality of test patterns to describe the
characteristics of the digital circuit and for inputting a plurality of input
signals to test the operation of digital circuit and a plurality of output signals
to describe the expected output of the digital circuit based on the plurality of
input signals;
an applying circuit to apply the input signals to test the operation of
the digital circuit to said test patterns to describe the characteristics of the
digital circuit to form a simulated output signal to indicate a response based
on said test patterns;
a comparator circuit to compare said simulated output signaI with the
output signals to describe the expected output of the digital circuit based on
the plurality of input signals to determine a difference between the simulated
output signal and said output signals, wherein the operation of the simulation
is stopped if said difference is greater than a threshold difference.
The prior art references of record relied upon by the examiner in rejecting the appealed
claims are:
Simoudis et al. (Simoudis) 5,016,204 May 14, 1991
Hyduke 5,051,938 Sep. 24, 1991
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