Appeal No. 1999-2747
Application 08/757,979
steps of." This limitation is met by the Lefsky disclosure8
of a cache memory wherein status bits for mapping out
defective cache cells and for controlling cache memory data
replacement are stored.
The first subparagraph of this claim reads: "identifying
a failing element in the storage array." Lefsky, discloses9
that if a cache cell experiences a failure, the failure is
detected by the read circuitry and a force bit is set to
indicate a defective cache cell. Thus, this section of the
claim is disclosed by Lefsky.
The third subparagraph of this claim reads: "setting a
flag to inhibit access to a portion of the array accessed by
the failing element." Lefsky discloses that when cache cell 10
failure is detected, a force bit is set to indicate a
defective cache cell and thereafter no data is stored in that
cache cell and its inputs are ignored. The force bit is the
herein claimed flag which inhibits access to a portion of the
8Column 1, lines 7-13.
9Column 5, lines 13-16.
10Column 5, lines 13-18.
9
Page: Previous 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Next
Last modified: November 3, 2007