Appeal No. 2000-0671
Application No. 08/909,507
column 2, lines 1-33, column 5, lines 13-20, and Figure 3 of Jarwala as disclosure of a
technique for testing at least one I/O connection of a circuit board simultaneously with
the testing of at least one device on the board which contains at least one first
boundary scan register, noting that Jarwala further teaches a serial test extension
module (STEM) which physically mates with the pins of an edge connector on the
circuit board through which the I/O connections to the board are made. Thus,
according to the examiner, Jarwala teaches an interface board 30 comprising a
connector, and a plurality of interfaces on a STEM 28 with a plurality of separate
sockets 32-32k for mating with edge connector 18 on a circuit board 10 so that a
connector and a plurality of interfaces coupled in series and in parallel receive a
plurality of boundary scan signals.
The examiner further cites column 5, lines 31-33, of Jarwala for devices 12-12n
being mounted on a board 10 with connector interface 18; and he cites column 5, lines
20-24, for an edge connector 18 on a circuit board 10 to allow different types of circuit
boards to be mated with STEM 28'. The examiner concludes that Jarwala thus teaches
at least one card comprising a socket and being removably coupled with one of a
plurality of interfaces.
Appellants argue, at page 6 of the brief, that Jarwala does not disclose a device
which can be used to program ISP devices and that Jarwala “pertains to only one ‘card’
3
Page: Previous 1 2 3 4 5 6 7 8 Next
Last modified: November 3, 2007