Appeal No. 2000-0702
Application 08/653,306
output signals being orthogonal to one another. A further
understanding of the invention can be achieved from the following
claim.
4. A circuit configuration for generating two output
signals being orthogonal to one another, comprising:
a delay device having an input to which an input signal is
applied, an output at which an output signal is available, and a
control input for controlling a time lag;
a multiplier device having inputs being coupled to the input and
the output of said delay device and having an output;
a device for low-pass filtering being connected between the
output of said multiplier device and the control input of said
delay device, said low-pass filter being directly connected to
said delay device; and
a master-slave toggle flip-flop following said multiplier device
and having outputs at which two output signals being orthogonal
to one another are available.
The Examiner relies on the following references:
Rein 5,015,872 May 14, 1991
Hamano et al. (Hamano) 5,066,877 Nov. 19, 1991
Naka1 2-125515 May 14, 1990
(Japanese)
Kono1 03-136515 Jun. 11, 1991
(Japanese)
Claim 4 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Rein in view of Naka or Kono.
1
1 English translation is enclosed with the decision.
2
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