Appeal No. 2000-1282
Application No. 08/813,140
said second error-encoded digital signal, while
simultaneously causing said error correcting circuitry to
error encode digital signals stored in the first portion
of said digital memory to form an error-encoded result
and store said error-encoded result into said first
portion of said digital memory, and
said control circuitry alternately performs said
first and second phases of said recording operation such
that said first period of time and said second period of
time are nonoverlapping.
The references relied on by the examiner are:
Glover et al. (Glover) 4,564,945 Jan. 14,
1986
Lang 4,963,995 Oct.
16,
1990
Lane et al. (Lane) 5,377,051 Dec. 27, 1994
Denissen et al. (Denissen) EP 0 553 515 A2 Aug. 4, 1993
(published European Patent Application)
Claims 1 through 3, 8 through 12, 25 through 27 and
31 through 34 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Denissen.
Claims 4 through 7, 13 through 22, 28 through 30 and
35 through 44 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Denissen in view of Lane.
Claims 23 and 45 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Denissen in view of Glover.
Claims 24 and 46 stand rejected under 35 U.S.C. § 103(a)
4
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