Appeal No. 2000-1985
Application No. 09/124,091
9. A multiplexer circuit comprising:
a first transistor coupled between a first predetermined voltage and
a node;
a second transistor coupled between a second predetermined
voltage and the node; and
a third transistor coupled between a third predetermined voltage
and the node, wherein said first, second and third transistors are
responsive to first, second and third clock signals, respectively such that
one of the first, second and third predetermined voltages is outputted at
the node, the first, second and third predetermined voltages being
different, and said first transistor is a mono-directional transistor and said
second transistor is a bi-directional transistor, and the second
predetermined voltage is less than the first predetermined voltage, and
greater than the third predetermined voltage.
The prior art references of record relied upon by the examiner in rejecting the
appealed claims are:
Takahashi et al. (Takahashi) 4,551,634 Nov. 05, 1985
Appellant’s admitted prior art (AAPA) as shown in Figures 1A-1C and Figure 2A-2B
Claims 9-21 stand rejected under 35 U.S.C. § 103 as being unpatentable over
Takahashi in view of AAPA.
Rather than reiterate the conflicting viewpoints advanced by the examiner and
appellants regarding the above-noted rejections, we make reference to the examiner's
answer (Paper No. 13, mailed Dec. 23, 1999) for the examiner's reasoning in support of
the rejections, and to appellants’ brief (Paper No. 12, filed Oct. 20, 1999) for
appellants’ arguments thereagainst.
2
Page: Previous 1 2 3 4 5 Next
Last modified: November 3, 2007