Appeal No. 2002-1938 Page 2
Application No. 09/292,959
that "approximately 25% of the computing capacity" is used for routine tasks. (Id. at 1-
2.) Even if the routine tasks were done by separate modules, add the appellants, "the
task of controlling the data transfer from and to the modules must still be handled by
the [digital] signal processor which would further impair its computing capacity." (Id.
at 2.)
Consequently, an object of the invention is to "optimize . . . the computing
capacity" of a DSP operating in an ASIC. (Spec. at 2.) More specifically, the ASIC
features a router connected between the DSP and other modules in the ASIC. The
router controls the transfer of data between the DSP and the other modules "without
blocking computing time of the processor." (Paper No. 7 at 2.) Because the DSP is
freed from having to control the data transfer, its computing capacity is conserved for
performing "more primary tasks." (Id.)
A further understanding of the invention can be achieved by reading the following
claim.
1. A single integrated circuit comprising:
a processor for processing data,
at least two modules each for processing data packets selected by
the processor according to a respective different operation process, and
Page: Previous 1 2 3 4 5 6 7 8 Next
Last modified: November 3, 2007