Appeal No. 1999-2701
Application No. 08/650,850
claims are directed to a technique for extending the range of
precompensation that a write precompensation circuit is able to
provide. In particular, a clock signal and the clock signal
delayed by a predetermined time are ORed together to provide a new
clock signal having an extended duty cycle, thereby permitting the
write precompensation circuit to produce a longer precompensation
delay.
Claim 15 is illustrative of the invention and reads as
follows:
15. A method for improving performance of a write precompensation
circuit comprising the steps of:
providing a clock signal;
delaying said clock signal to produce a delayed clock signal;
forming an extended duty cycle clock signal based on the
logical OR of said clock signal and said delayed clock signal.
The Examiner relies on the following prior art:
Ziperovich et al. (Ziperovich) 5,493,454 Feb. 20, 1996
(filed Oct. 4, 1994)
Claims 15-17 and 32-34 stand finally rejected under 35 U.S.C.
§ 102(e) as being anticipated by Ziperovich.
Rather than reiterate the arguments of Appellants and the
Examiner, reference is made to the Brief (Paper No. 12) and Answer
(Paper No. 13) for their respective details.
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