Appeal No. 2001-1352
Application 08/802,828
As disclosed and depicted in specification Figure 6, in
response to the generation of an insert signal from the insert
key 8 in Figure 1, a pointing vector generator generates a block
of pointing vectors 29 in Figure 6 having a respective first
address signal (n) which specifies the location where dictated
insert should be inserted in the data file (F), and a second
address signal (p) which indicates the beginning address of an
available portion of addressable memory for actually storing the
insert itself. Although not set forth in independent claims 1
and 13 on appeal, a third address vector location (q) identifies
the ending address of the dictated insert.
It is thus apparent that the dispute revolves around the
stated first and second address signals generated by the claimed
pointing vector generator means in representative independent
claim 1 on appeal. Corresponding features are recited in
independent claim 13 on appeal as well. It is this clause at the
end of representative claim 1 on appeal that appellant rightly
argues that the examiner has not proven to be taught or suggested
among the prior art applied. Appellant's arguments do not
dispute the proper combinability within 35 U.S.C. § 103 of the
references relied upon, but only assuming a proper combination is
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