Appeal No. 2001-1451
Application No. 09/166,656
1. An integrated circuit structure in a device package,
comprising:
a package substrate including a first set of bonding pads on
a first surface and a second set of bonding pads on a second
surface;
a device substrate having an exposed back surface, a front
surface, and a circuit interconnect layer disposed near the front
surface and having a plurality of electronic components formed
therein and a plurality of input/output pads connected to
selected ones of the components and to respective ones of the
second set of bonding pads of the package substrate;
an active region disposed in the device substrate between
the interconnect layer and the back surface; and
an electrically conductive probe extending from the back
surface of the device substrate to the active region and
terminating at the active region, the probe including a signal-
coupling tip adapted to electrically couple to the active region.
The prior art references of record relied upon by the
examiner in rejecting the appealed claims are:
Filippazzi et al. (Filippazzi) 3,787,252 Jan. 22, 1974
Chatterjee 4,889,832 Dec. 26, 1989
Kazama 5,291,129 Mar. 01, 1994
Gaul et al. (Gaul) 5,807,783 Sep. 15, 1998
(filed Oct. 07, 1996)
Appellants' admitted prior art at pages 1-5 of the specification
and Figure 1 (AAPA)
Claims 1 and 2 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Filippazzi in view of AAPA.
Claims 3 through 17 and 19 through 23 stand rejected under
35 U.S.C. § 103 as being unpatentable over Filippazzi in view of
AAPA and Chatterjee.
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