Appeal No. 2001-2100
Application No. 08/833,302
condition cell selection protocol in the following language
(similar recitations of which appear in the other independent
claims 3, 6, and 7):
... when data cell sent from the ATM layer control
unit is delivered thereto, the selector means
outputs the data cell, when output of test cell is
designated and no data cell exists, the selector
means outputs the test cell which the test cell
generating circuit outputs, and when no data cell
exists and output of the test cell is not designated,
the selector means outputs the idle cell which the
idle cell generating circuit outputs.
We find no disclosure in the Yoshimura reference, primarily
relied on by the Examiner as teaching the claimed selection
protocol, that would satisfy the requirements of the appealed
claims. In particular, although Yoshimura suggests (e.g., column
3, lines 36-39) that test cells are generated in relation to the
timing of idle cells, we find no apparent disclosure in Yoshimura
of the generation of idle cells on the condition that no data
cell exists and there is no designation of the output of test
cells as claimed.
We also agree with Appellant (Reply Brief, pages 2 and 3)
that the Examiner has improperly disregarded the claim language
directed to the claimed loop-back circuit feature. Our reviewing
courts have held that, in assessing patentability of a claimed
invention, all the claim limitations must be suggested or taught
-6–6
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