Appeal No. 2001-2447
Application No. 09/085,143
Appellants, conventional models use a generic wire load model for estimating capacitance and
resistance, which frequently lack sufficient accuracy (specification, pages 4 & 5). In the
disclosed design of an IC, having several metal layers, a technology-independent description of a
system is generated which specifies a signal and a selected metal layer for the signal
(specification, page 6).
Representative independent claim 1 is reproduced below:
1. A method for designing an electronic circuit to be implemented on an
integrated circuit die which includes plural metal layers, the method comprising:
a generating step of generating a technology-independent description of a
system, the technology-independent description specifying a signal and a selected metal
layer for the signal.
The Examiner relies on the following reference in rejecting the claims:
Rostoker et al (Rostoker) 5,623,418 Apr. 22, 1997
Claims 1-6 stand rejected under 35 U.S.C. § 102(b) as being anticipated by Rostoker.1
We make reference to the answer (Paper No. 13, mailed March 13, 2001) for the
Examiner’s reasoning, and to the appeal brief (Paper No. 12, filed December 18, 2000) and the
reply brief (Paper No. 14, filed May 14, 2001) for Appellants’ arguments thereagainst.
1 In the answer, the 35 U.S.C. § 102(e) rejection of claims 1-30 as being anticipated by Luk et al. (U.S.
Patent No. 5,883,814) or Rostoker et al. (U.S. Patent No. 5,808,330), the 35 U.S.C. § 102(b) rejection of claims 1-
30 as being anticipated by Huang (U.S. Patent No. 5,568,395), the 35 U.S.C. § 102(b) rejection of claims 7-30 as
being anticipated by Rostoker et al. (U.S. Patent No. 5,623,418), and the 35 U.S.C. § 103 rejection of claims 1-30
over De Camp et al. (U.S.) Patent No. 5,761,080) or Folta et al. (U.S. Patent No. 5,831,870) in view of taking of
official notice, as stated in the final rejection (Paper No. 7, mailed March 13, 2000), have been withdrawn by the
Examiner.
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