Appeal No. 2002-0003
Application No. 09/056,794
12. A process of production of a semiconductor memory device having
a memory array including memory cells and a peripheral circuit on one substrate
comprising:
forming an interlayer insulating layer covering said memory array and
peripheral circuit;
forming said memory cells;
exposing a surface of diffusion regions in the peripheral circuit after
forming said memory cells;
forming a covering conductive layer on the exposed surface of the
diffusion regions in the peripheral circuit; and
flattening by chemical mechanical polishing.
The prior art of record relied upon by the examiner in rejecting the appealed
claims is as follows:
Suwanai et al. (Suwanai) 5,025,741 Jun. 25, 1991
Iijima et al. (Iijima) 5,903,053 May 11, 1999
Claims 11-18 stand rejected under 35 U.S.C. § 103 as being unpatentable over
Suwanai in view of Iijima.
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