Appeal No. 2002-0550
Application No. 09/264,770
Claim 1 is illustrative of the claimed invention, and it
reads as follows:
1. A method for producing a logic cell, the method
comprising the following steps:
(a) generating a timing model for the logic cell, including
the following substeps:
(a.1) selecting output load indices (Load1, Load2,....,
Loadm) which specify output load for the first logic cell,
(a.2) selecting input ramp indices (IR1, IR2,
....,IRn)which specify input ramp for the first logic cell,
(a.3) generating baseline output ramp values
(ORb1[j,k]) for each output load index (Loadj) and input ramp
index (IRK) pair,
(a.4) scaling the output load indices by a first
scaling factor (8),
(a.5) scaling the input ramp indices by a second
scaling factor (D), and
(a.6) generating scaled output ramp values (ORscaled
[j,k]) for each scaled output load index and scaled input ramp
index pair, wherein a numerical value of ORscaled [j,k] represents
a value of output ramp at new Process, Power supply, Temperature
conditions when the output load for the first logic cell is equal
to 8* Loadj and the input ramp for the first logic cell is equal
to D* IRk; and,
(b) building the logic cell based on the timing model
generated in step (a).
The references relied on by the examiner are:
Misheloff 5,559,715 Sept. 24, 1996
McNelly et al. (McNelly) 5,625,803 Apr. 29, 1997
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