Ex Parte Kern et al - Page 7




          Appeal No. 2002-1173                                                         
          Application No. 09/510,640                                                   


          In re Paulsen, 30 F.3d 1475, 1478-79, 31 USPQ2d 1671, 1673 (Fed.             
          Cir. 1994).  Anticipation is established only when a single prior            
          art reference discloses, expressly or under the principles of                
          inherency, each and every element of a claimed invention as well             
          as disclosing structure which is capable of performing the                   
          recited functional limitations.  RCA Corp. v. Applied Digital                
          Data Sys. Inc., 730 F.2d 1440, 1444, 221 USPQ 385, 388 (Fed. Cir.            
          1984).                                                                       
               Upon a review of Hsieh, we agree with Appellants that the               
          reference fails to teach replicating the operations performed                
          prior to the reset signal.  The power supply voltage sensing                 
          circuit of Hsieh generates a reset signal not only when the power            
          supply voltage is first applied to the circuit, but also when the            
          power supply voltage level falls below a selected value (col. 1,             
          lines 11-14).  The reset signal holds the integrated circuit in a            
          known state until the power supply voltage returns to its                    
          selected value where the integrated circuit may function reliably            
          (col. 4, lines 3-9).  This arrangement differs from the claimed              
          “repeating operations of the integrated circuit which ... have               
          (possibly) been influenced by the dip in the supply voltage”                 
          since the reset signal of Hsieh, similar to its power-on reset,              
          clears all the data to the initial state and waits for the next              

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