Appeal No. 2002-1241
Application No. 08/883,141
OPINION
In applying Reese against the instant claimed invention, the examiner contends that in
Figure 2 of Reese, echo canceler 34 comprises echo canceler modules which comprise a “pool of
echo cancellers.” The examiner also points out that each echo canceler module 46 has an input
64 and an output 66 so that the reference discloses a “pool of echo cancellers, each echo canceller
having an input and an output.”
The examiner identifies a “pool switch matrix” in Reese as the cross point switch 44,
which has a first set of ports (signal line 54) and a second set of ports (signal line 60). It is the
examiner’s position that the claimed “control circuitry directing the pool switch matrix...” is met,
in Reese, by CPU 45 which controls operation of the cross point switch 44. The examiner
explains, with reference to Figure 2 of Reese, that
DSO signal line 60 (B-channel) is routed to a path multiplexer 56 from a cross point
switch 44. If echo canceler is not needed [on the B-channel] the path
multiplexer 56 routes the signal line 60 to signal line 62. Alternatively, if echo canceler
is required, the path multiplexer 56 routes the signal line 60 to one of available echo
canceler modules 46 via a signal line 64 and output on a signal line 66 to signal line 62.
See col. 5, lines 37-52 (answer-page 18).
-4-
Page: Previous 1 2 3 4 5 6 7 8 9 10 Next
Last modified: November 3, 2007