Page 3
Appeal No. 2002-1854
Application No. 09/163,874
The appellant’s invention is directed to a method for the linear configuration of
metallic fuse sections which provide a bit combination that represents a characteristic of
a circuit on a wafer. As explained in the opening pages of the specification, selected
fuse sections in a linear arrangement are burned (severed) to set the characteristics of
circuits. These fuse sections can only be accessed for such action when the polyimide
passivation layer that covers them after they are assembled into an arrangement has
been removed by exposure and etching. According to the appellant, while under
optimum process conditions the polyimide layer is completely removed from all of the
fuse sections in an arrangement, under unfavorable conditions it may be that the layer
remains over the fuse section that represents the most significant bit (number) of a bit
combination that will set the circuit. This prevents that fuse section from being burned
without further actions being taken to uncover it, which complicates the manufacturing
process. The appellant states that it is common for the polyimide layer not to be
removed from the end portions of a line of fuse sections in an arrangement, and
therefore if a fuse section that must be burned in order to construct the circuit is located
in an end portion, it cannot be accessed in order to be burned. See pages 12, 8 and 9;
Figures 2 and 3. The objective of the appellant’s invention is to minimize this problem,
which is accomplished by placing a fuse section that has been selected as being
significant to the establishment of the desired circuit and placing it at a location other
than in the end portion of the configuration of fuse sections.
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