Appeal No. 1998-0940
Application No. 08/085,605
advantage of enlarging printing resolution with out [sic,
without] increasing memory size” (principal answer, page 5).
The examiner employs a third combination of all three of
these references in rejecting claims 3, 4, 7, 12 and 14 under
35 U.S.C. § 103, finding now that Shimura discloses the invention
but for the “while” limitation, i.e., that the step of inputting
the second bit-mapped field of image data in the frame-store is
performed “while” performing steps (e), (f) and (g) on the first
bit-mapped field of image data. The examiner then relies on
Kadowaki and Suzuki for teaching the performance of writing/
inputting associated functions for a second image while
performing reading/outputting associated functions for a first
image of a bit-mapped memory, as claimed. In the examiner’s
view, it would have been obvious to adapt the system of Shimura
to perform reading/outputting associated functions while
performing writing/inputting functions “in order to obtain the
advantage higher operating speeds that would result” [sic]
(principal answer, page 6).
The examiner produces a table, at pages 7-12 of the
principal answer, purporting to show the correspondence between
the claimed elements and the elements disclosed by the
references.
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