Appeal No. 2002-1672
Application No. 09/412,124
Rejection under 37 CFR § 1.196(b)
We make the following new ground of rejection using our
authority under 37 CFR § 1.196(b).
Claim 1 is rejected under 35 U.S.C. § 103(a) as being
unpatentable over Nakano (U.S. Patent No. 5,146,586) in view of
Bridges (U.S. Patent No. 5,809,293), each of record, and cited
and applied by the Examiner in this appeal. Nakano discloses, in
particular in the description beginning at column 3, line 21, the
storing in tracer memory 7 of instruction address information
occurring before an “exceptional event,” in this case an event
which “triggers” the execution of a failure recovery procedure.
It is further clear from the description at column 3, lines 51-62
in Nakano that instruction address information related to the
execution of the failure recovery procedure, which recovery
procedure is initiated after the occurrence of the “exceptional
event,” is also stored in tracer memory 7. This is apparent
since, as further disclosed in Nakano, on occurrence of a second
“exceptional event” during the execution of the failure recovery
procedure, the execution history of the failure recovery
procedure is preserved in tracer memory 7.
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