Appeal No. 2002-1743
Application No. 09/047,866
Appellants first argue that the applied combination of references fails to disclose
the claimed digital signal processor (DSP) that is coupled to two registers that are each
coupled to a receive and transmit signal path with the digital signal processor updating
the respective peak signal values based on the receive/transmit signal level. However,
the examiner explains, quite reasonably, in our view, that Cleary discloses a digital
signal processor for updating peak signal values in a register to provide for the peak
value detected and that a signal processor is “necessary” to process the signals.
Appellants argue that Cleary utilizes a comparator 36, which is not a DSP, to
compare the comparator’s storage value with the storage value of storage register 32
that was previously clocked into register 32 by control circuit 30. Appellants’ argument
is that Cleary only discloses one register versus the two registers of the instant claimed
invention; that Cleary’s comparison only occurs when BCD counter reaches zero after
counting through a 100-element display; and that register 32 is not DSP accessible nor
controlled.
Appellants’ arguments are tantamount to requiring a bodily incorporation of the
elements of Cleary into the structure of Miter. This is not required under 35 U.S.C.
§103. The test of obviousness is not whether features of a secondary reference may
be bodily incorporated into the primary reference’s structure, nor whether the claimed
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