Appeal No. 2003-0302
Application No. 09/107,539
Claims 1 through 6, 9 through 13, 17, 21 through 23, 25
through 27, 30, 31 and 33 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Chin in view Yanai.
Claims 7, 8, 14 through 16, 18 through 20, 24, 28, 29, 32
and 34 through 36 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Chin in view of Yanai and Blickenstaff.
Reference is made to the briefs (paper numbers 20 and 22)
and the answer (paper number 21) for the respective positions of
the appellants and the examiner.
OPINION
We have carefully considered the entire record before us,
and we will reverse the obviousness rejections of claims 1
through 36.
In the alternative embodiment of Chin (i.e., Figure 12), a
single transaction processor 1210 performs the function of a
host, and controls data flow between a storage unit 12, 14 in a
primary loop 10 and another storage unit 32, 34 in a secondary
loop 26. A first parallel processor 1216 and a second parallel
processor are provided for control of the primary loop 10 and the
secondary loop 26, respectively.
The examiner acknowledges (answer, page 4) that “Chin does
not specifically teach bypassing the host while transferring data
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