Appeal No. 2003-0312
Application No. 08/871,199 Page 8
charge of the intermediate integration circuits, and control
means to modify the contents of the intermediate integration
circuits when at least one of the charges exceeds a given value
(col. 1, line 60 through col. 2, line 2). Figure 1 discloses a
detector constituted by an array of sensors A1, Ai...An. Each of
the sensors is connected by a sequence of circuits, to
multiplexer K, provided with an output S. The output of sensor
Ai is connected to the input of coupling circuit Bi, which is
controlled by clock H. The output of circuit Bi is connected to
the input of an intermediate integration circuit Di, which is
associated with a potential barrier Ei. A port of intermediate
integration circuit is connected to an input of transfer circuit
Gi, which is controlled by clock H. The output of transfer
circuit Gi is connected to the input to main integration circuit
Ji., the output of which is connected to multiplexer K. A port
of the potential barrier Ei is connected to a measuring circuit M
and to a switch N. Inverter Q, controls the potential barriers
such as Ei, and the input of switch N (col. 2, lines 15-59). In
the example described, potential barrier Ei has an FET
transistor, the drain of which is connected to measuring circuit
M and switch N. The gate receives the signal Cc, as shown in
figure 2. Fouilloy further discloses that the height of the
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