Appeal No. 2003-0376
Application 09/364,281
claimed. Appellants also respond that the combined references
fail to teach the assignment of tasks to nodes based upon hashed
addresses or a hashing circuit that performs such assignment.
Appellants argue that a hashing selection circuit is not
inherently present in the applied prior art [reply brief].
We will not sustain the examiner’s rejection of claims 1,
3, 5-7, 9, 11-13, 15, 17 and 18 for essentially the reasons
argued by appellants in the briefs. In our view, the examiner
has done nothing more than find a first reference that teaches
hardware reconfiguration with absolutely no suggestion of address
hashing with a second reference that broadly teaches hashing
addresses for a cache memory with absolutely no other indicated
uses. The examiner has then attempted to cobble a rejection by
picking and choosing selected parts of these references and by
dismissing specific features of the claimed invention as being
well known and inherent. The examiner’s first major mistake is
to assume that if addressing is present, then hashing must also
necessarily be present. There is no requirement that hardware
addressing make use of a hashing algorithm. The second major
mistake made by the examiner is to assume that the general
hashing scheme used by Eberhard for cache accessing automatically
suggests using a hash addressing scheme for the node accessing
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