Appeal No. 2003-0882 Page 4
Application No. 09/911,198
Co. V. Ireco Inc., 190 F.3d 1342, 1347, 51 USPQ2d 1943, 1947
(Fed. Cir. 1999); In re Paulsen, 30 F.3d 1475, 1478-79, 31
USPQ2d 1671, 1673 (Fed. Cir. 1994).
The examiner’s position (answer, page 4) is that Jung
clearly discloses a circuit (Fig. 2) where a latch (Q5-Q8)
communicates the input signal to the output terminal when the
circuit is not in sleep mode (Q10 HIGH), and then in response to
the circuit being in sleep mode (Q10 LOW), furnishes another
signal to the output terminal indicative of a programmed value.
The examiner equates a HIGH relative voltage applied to EN
(source terminal of NMOS Q10) to the non-sleep mode, and a LOW
relative voltage to the claimed sleep function (id.). Thus, the
examiner asserts that when the EN signal is LOW, Jung is acting
in a sleep mode because a change in the value DATA at the input
terminal creates no corresponding change at the output terminal
as in the claimed invention (answer, pages 7 and 8). Due to the
latch structure of Jung, the value at the output terminal, prior
to a diametric change on the EN terminal from a HIGH to LOW, is
retained (id.).
Appellants rebut examiner’s contention that a signal could
be furnished to the output terminal of Jung when Q10 is disabled,
where the path to ground for all circuitry is removed (brief,
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