Ex Parte Akimoto et al - Page 3




          Appeal No. 2003-1663                                                        
          Application 09/975,934                                                      

          (Paper No. 14) (pages referred to as "RBr__") for a statement of            
          appellants' arguments thereagainst.                                         
                                       OPINION                                        
               Same-invention double patenting under 35 U.S.C. § 101 means            
          identical subject matter.  In re Vogel, 422 F.2d 438, 441,                  
          164 USPQ 619, 621 (CCPA 1970).  "A good test, and probably the              
          only objective test, for 'same invention,' is whether one of the            
          claims could be literally infringed without literally infringing            
          the other.  If it could be, the claims do not define identically            
          the same invention."  Id. at 441, 164 USPQ at 622.  Same-                   
          invention double patenting cannot be overcome by filing a                   
          terminal disclaimer.                                                        
               Claims 1-15 of the present application are identical to                
          claims 1-9 and 11-16, respectively, of the '973 patent, except              
          that independent claims 1, 10, 14, and 15 of the present                    
          application recite an "AND functional circuit" whereas claims 1,            
          11, 15, and 16, respectively, of the '973 patent recite an "AND             
          logical circuit."  The AND circuit is described in connection               
          with the pixel array in Fig. 2.  The pixel array contains an AND            
          gate circuit 47 for driving the gate of the TFT switch 48, the              
          AND gate formed by a CMOS process, where the input terminals of             
          the AND gate circuit 47 are connected to a vertical direction               
          gate selection line 50 and a horizontal direction gate selection            


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