Appeal No. 2004-1402
Application No. 09/383,478
BACKGROUND
Appellants’ invention relates to improved arithmetic circuits for use with the
residue number system (RNS). An understanding of the invention can be derived from
a reading of exemplary claim 1, which is reproduced below.
1. A modulo mi adder for use with an RNS, said adder comprising:
a modulo mi barrel shifter; and
a dynamic storage unit coupled to the barrel shifter, the dynamic storage unit
storing the output of the barrel shifter.
The prior art references of record relied upon by the examiner in rejecting the
appealed claims are:
Ishibashi 5,208,480 May 4, 1993
Chren, W. A., “One-Hot Residue Coding for Low Delay-Power Product CMOS Design,”
45 IEEE Transactions on Circuits and Systems -Analog and Digital Signal Processing
no. 1, 303-313 (March 1998)
Appellants’ Admitted Prior Art - (AAPA) See Figures 2(a) and 2(b) and associated text.
Claims 1-9 and 31-36 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over AAPA in view of Ishibashi. Claims 28-30 and 37-39 stand rejected
under 35 U.S.C. § 103(a) as being unpatentable over AAPA and Ishibashi further in
view of Chren.
Rather than reiterate the conflicting viewpoints advanced by the examiner and
appellants regarding the above-noted rejections, we make reference to the examiner's
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