Appeal No. 2004-1834
Application No. 10/158,885
1. A method of processing partial wafers comprising the step of:
making all partial wafer cuts perpendicular to the wafer flat with all
partial wafer cuts following a cut sequence where the first cut section is
with a reference die and the other cut sections are in the numerical order
from right to left with the first partial wafer of the full wafer having a
reference die;
identifying a pseudo reference die for each partial wafer not having
a reference die which die is the first die in the bottom right;
moving wafer table to the last left column of the partial wafer and
determining the coordinate;
storing the coordinate of the last left column in a wafer map data file;
removing all dies from the wafer map that are not part of the partial
wafer using said coordinate; and
performing picking and placing dies.
The examiner relies on the following reference:
Balamurugan 6,174,788 Jan. 16, 2001
The examiner also relies on admitted prior art (APA) described at paragraph 3 of
the instant specification.
Claims 1-14 stand rejected under 35 U.S.C. §103. As evidence of obviousness,
the examiner offers Balamurugan with regard to claims 1-4, and 6-11, adding APA with
regard to claims 5, and 12-14.
Reference is made to the briefs and answer for the respective positions of
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