Appeal No. 2005-0239
Application No. 10/145,421
1. A method of producing a CMOS integrated circuit
comprising the steps of:
providing a semiconductor substrate;
forming a gate dielectric on an active area on the
substrate;
depositing a polysilicon layer on top of the gate
dielectric;
implanting a P-type dopant into the polysilicon layer;
patterning an N-doped gate region on said polysilicon layer, the
remainder of said polysilicon layer remaining a P-doped region;
implanting an N-type dopant into the N-doped gate region;
patterning the gate regions;
etching the gate regions; and
then performing a gate anneal.
2. The method of claim 1 wherein said step of implanting an
N-type dopant also includes implanting a P-type dopant with the
resulting doping level being N-type.
3. The method of claim 2, further comprising the step of
performing an electrical critical dimension test on the gate
following gate anneal.
3
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