Appeal No. 2005-0429 Page 2
Application No. 09/872,209
also provides the user the option to take control of every aspect of scan timing
externally in an FPGA if the user requires the modes of operation to be extended
for advanced imaging. Appellants’ specification page 3, lines 12-24.
Claim 1 is representative of the claimed invention and is reproduced as
follows:
1. An improved CMOS integrated imager system having an array of pixel
areas with at least one control area, wherein said pixel areas include a plurality of
light collecting elements which each receive light and store electronic information
in an amount indicative of an amount of light received during an integration
period, with the control area having an internal timing element, wherein the
improvement comprises:
a user interface for receiving a plurality of data, address, and control
signals, said interface configured to receive from a user a mode signal for setting
the system in one of a first operating mode or a second operating mode
characterized in that the first operating mode uses the internal timing element to
control timing operation of the system and the second operating mode bypasses
the internal timing element to control timing operation of the system.
References
The references relied on by the Examiner are as follows:
Noble et al. (Noble) 5,760,636 Jun. 2, 1998
Shinohara EP 0942592 Sep. 15, 1999
Rejections At Issue
Claims 1-6 stand rejected under 35 U.S.C. § 103 as being obvious over
the combination of Shinohara and Noble.
Claims 7-9 stand rejected under 35 U.S.C. § 103 as being obvious over
Shinohara.
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