Appeal No. 2005-0449
Application No. 09/498,559
inductor that is biased using a voltage generated on said
integrated circuit that is outside the range of the voltage
supplied by a power supply off of said integrated circuit for
operating said integrated circuit.
The references set forth below are relied upon by the
examiner as evidence of anticipation and obviousness:
Vargha 6,069,516 May 30, 2000
(filed Apr. 28, 1998)
Ko et al. 6,02,496 Feb. 22, 2000
(filed Jun. 3, 1998)
Claims 14-19 are rejected under 35 U.S.C. § 102(b) as being
anticipated by Vargha. On page 4 of the answer, the examiner
expresses his anticipation position as follows:
Vargha discloses in Figure 1 a circuit comprising:
- a metal oxide semiconductor (MOS) transistor (12);
- a beyond voltage generator (10) which generates a
beyond voltage (Vcc+V1) that is either greater than the
highest voltage (Vcc) or less than the lowest voltage
being supplied to said integrated circuit by a power
supply; and
- wherein said MOS transistor (12) is coupled to said
beyond voltage generator (10) so as to bias said MOS
transistor with said beyond voltage (Vcc+V1) and said
MOS transistor (10) is adapted to operate as said
active inductor.
Claims 1-13 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Vargha in view of Ko. The examiner’s
obviousness conclusion is set forth on page 5 of the answer and
reads as follows:
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