Appeal No. 2005-0859 Page 3
Application No. 10/015,965
claim 9 requires a hardware circuit that includes means for
implementing one of a direct convention and an indirect
convention of an order of bits of a word as a function of a value
of a convention signal.
The examiner argues that Chiang’s data communication between
memory unit 11 and the processors (ECD processor 13 and ECC-P
processor 15; figure 1) is a “conventional signal” (answer,
pages 3-4). The appellant’s claims 1, 5 and 9, however, do not
recite a “conventional signal” but, rather, recite a “convention
signal”. The appellant’s specification discloses a convention
bit that is generated from either a direct convention signal or
an indirect convention signal and has a value of 0 when the
direct convention is used and 1 when the indirect convention is
used (page 4, line 32 - page 5, line 7). The portion of Chiang
relied upon by the examiner for a disclosure of a “conventional
signal” (col. 1, line 66 - col. 2, line 26) does not disclose a
convention signal. The portion of Chiang relied upon by the
examiner for a disclosure of a hardware circuit that allows an
inversion of an order of bits of a word as a function of a value
of a convention signal during a transfer of a word between an
electronic module and a microprocessor (figure 7; col. 6, line 59
- col. 7, line 48) does not disclose either a convention signal
or allowing an inversion of an order of bits of a word as a
function of a value of a convention signal during a transfer of a
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