Appeal No. 2005-1503
Application No. 10/165,888
1. A method of fabrication of an integrated circuit, comprising
the steps of:
providing a substrate;
forming a high-k dielectric layer on said substrate;
amorphizing said dielectric layer by ion bombardment;
forming gate material on said amorphized dielectric layer; and
forming gates from said gate material.
3. The method of claim 1, wherein:
said ion bombardment of step (c) of claim 1 is exposure to a
plasma.
7. The method of claim 1, further comprising prior to said
forming gate material of step (d) of claim 1, forming dummy gates
on said dielectric layer and removing said dummy gates.
9. The method of claim 2, wherein:
said metal silicate is within one of the two rectangular regions
bounded by broken lines in Figure 4.
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Last modified: November 3, 2007