Appeal No. 2005-1576
Application No. 09/885,217
Briefs have not been considered and are deemed to be waived [see
37 CFR § 41.37(c)(1)(vii)].
Appellants’ arguments in response assert that the Examiner
has not shown how each of the claimed features are present in the
disclosure of Morishita so as to establish a case of
anticipation. In particular, Appellants contend that, in
contrast to the claimed invention, “Morishita fails to teach a
voltage reference circuit that includes a unity gain amplifier
for producing a reference voltage in response to a reference
signal.” (Brief, page 4).
After careful review of the Morishita reference in light of
the arguments of record, however, we are in general agreement
with the Examiner’s position as stated in the Answer. We find no
arguments from Appellants that convince us of any error in the
Examiner’s position which, considering the entire circuitry
illustrated in Figure 17 of Morishita as a voltage reference
circuit, asserts that the amplifier circuit comprising elements
CMP and DT in Morishita is a unity gain amplifier. We further
agree with the Examiner that Morishita’s unity gain amplifier
produces a reference voltage as claimed since the reference
voltage Vref is maintained at the internal power supply voltage
INVcc level.
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