Appeal No. 2005-2150
Application No. 10/407,084
BACKGROUND
The invention relates to efficient fabrication of a microelectronic product within
multiple microelectronic product fabrication facilities. Representative claim 1 is
reproduced below.
1. A method for fabricating a microelectronic product comprising:
providing a plurality of microelectronic fabrication facilities comprising a
plurality of tools employed for fabricating a single microelectronic product, the
plurality of tools being divided into a series of comparable tool groups;
determining for the plurality of tools a corresponding plurality of tool
utilization factors when fabricating the single microelectronic product within the
plurality of microelectronic fabrication facilities;
comparing a plurality of tool utilization factors for a specific comparable
tool group to define an optimized tool utilization factor for the specific comparable
tool group; and
developing and implementing revised operating procedures for the
plurality of tools within the specific comparable tool group such that each tool
within the specific comparable tool group operates at a tool utilization factor
which approximates the optimized tool utilization factor for the specific
comparable tool group.
The examiner relies on the following references:
Burdick et al. (Burdick) 5,889,674 Mar. 30, 1999
Kraft 5,528,510 Jun. 18, 1996
Nakamura et al. (Nakamura) US 6,198,981 B1 Mar. 6, 2001
Martin US 6,259,959 B1 Jul. 10, 2001
Michael Quirk et al. (Quirk), Semiconductor Manufacturing Technology, Instructor’s
Manual, Prentice Hall College Div., ISBN 0130815209, pp. 1-68 (Dec. 2000).
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