Appeal No. 2005-1995
Application 09/133,741
We agree with appellant on both arguments. The vertex look
up table (VLUT) 304 in Figs. 3 and 5A stores input and output
vertices of a primitive. However, the vertex RAM 306 also stores
input and output vertices of the primitive (see col. 11,
lines 59-62: "the first four memory locations of VRAM 306 store
the input vertices of the input primitive, and are not
overwritten during ... clipping," and col. 12, lines 8-10: "The
clipper 308 ... writes the output vertices into the VRAM 306),
although not in an ordered list as in VLUT 304. Therefore, the
circuit does not use only a single buffer to store input and
output vertices as claimed.
The operation of the VLUT 304 does not suggest use of a
circular (ring) buffer. A circular buffer is a first-in, first-
out (FIFO) buffer that it uses head and tail pointers to indicate
write and read memory locations. The memory locations "wrap"
around to create a circular list of addresses. Data is added to
the location pointed to by the write pointer and is read from the
location pointed to by the read pointer. The VLUT 304 does not
operate in this manner. Referring to Fig. 5A, "[w]hen the
clipper 308 is called, the vertices in the output list are
shifted into the corresponding locations in the input list and
the output list is cleared" (col. 12, lines 4-6). This does not
act like a circular buffer. Rossin indicates that "[t]he VLUT
304 is preferably implemented in a double buffered RAM" (col. 11,
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