Ex Parte Takeno - Page 2



          Appeal No. 2006-1176                                                        
          Application No. 09/926,202                                                  
                               APPEALED SUBJECT MATTER                                
               The subject matter on appeal is directed to a process for              
          forming an epitaxial semiconductor wafer having internal                    
          microdefects, without causing external microdefects in a device             
          formation region (the vicinity of a top surface) of the wafer.              
          See the specification, pages 1-4.  The internal microdefects                
          “work as gettering sites that capture heavy metal impurities and            
          others by an action of a so-called internal gettering (IG).”  See           
          the specification, pages 1-2.  Details of this process are                  
          recited in representative claims 6 and 102 which are reproduced             
          below:                                                                      
               6. A manufacturing process for a silicon epitaxial wafer               
               comprising the steps of:                                               
                    forming an epitaxial layer on a silicon substrate with            
               an interstitial oxygen concentration in a range of from                
               4 x 1017/cm3 to 10 x 1017/cm3 at a temperature of 1000_ C or           
               higher to obtain a silicon epitaxial wafer; and                        
                    applying heat treatment to the silicon epitaxial wafer            
               at a temperature in a range of from 450_ C to 750_ C;                  
                    thereby forming new oxygen precipitation nuclei and               
               increasing bulk defect density, without reducing internal              
               gettering.                                                             
               10. The manufacturing process for a silicon epitaxial wafer            
                                                                                     
               2 For purposes of this appeal, we limit our discussion to              
          specifically argued claims 6 and 10 consistent with 37 CFR                  
          _ 41.37(c)(1)(vii)(2004).                                                   


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