Appeal No. 2006-1726
Application No. 09/725,849
We note that claim 18 reads in part as follows:
“ a gate driver, including a plurality of gate drive
circuits connected in series, to apply a gate pulse
signal to the TFT connected to the pixel element, the
gate pulse signal having at least two gate pulses
within a one frame interval; and a data driver to apply
a video data signal to the pixel element in accordance
with the gate pulse signal to charge the pixel
element.”
At page 9, lines 9- 29, Appellants’ specification states:
As shown in Fig. 10, the gate driver 26 includes k gate
drive integrated circuits GD-IC1 to GD-ICk each having
a plurality of shift registers and connected in
cascade. As shown in Fig. 11, the gate drive
integrated circuits GD-IC1 to GD-ICk respond to a start
pulse SP generated during each frame, e.g., every half
period of each frame, to sequentially generate the gate
pulse GP. The start pulse SP is generated at the
beginning of each frame. The ON data of the video data
signal Vdata is synchronized with the start pulse SP to
be applied to the data lines DL1 to DLn. The first to
Kth gate drive integrated circuits GD-IC1 to GD-Ick
respond to the start pulse SP to sequentially generate
the gate pulse GP. Thus, the start pulse SP is
generated again in the middle of each frame. The OFF
data of the video data signal Vdata is synchronized
with the start pulse SP to be applied to the data lines
DL1 to DLn. The first to Kth gate drive integrated
circuits GD-IC1 to GD-Ick respond to the start pulse SP
to sequentially generate the gate pulse GP.
Accordingly, the liquid crystal pixel cells charge the
off data at the beginning half of the frame.
Thus, the claim does require a gate driver having a
13
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