Ex Parte Harris - Page 2




              Appeal No. 2006-2332                                                                                     
              Application No. 09/751,610                                                                               

                                                   BACKGROUND                                                          
                     The invention relates to electronic control systems, in particular precision phase                
              generators for generating multiple phase clocking signals from a single phase clock                      
              signal.  Representative claim 20 is reproduced below.                                                    
                     20.    A method for generating at least two clock signals displaced from each                     
                     other by a predetermined phase shift of 360//2N, where N is a positive integer,                   
                     the method comprising:                                                                            
                            applying a clock signal to a signal input of a phase lock loop circuit at a                
                     desired clock frequency;                                                                          
                            applying a feedback signal to a second input of the phase lock loop circuit;               
                            generating an output signal of the phase lock loop circuit having a                        
                     frequency of 2NF0;                                                                                
                            coupling the output signal of the phase lock loop circuit to a clock input of              
                     each JK flip-flop of a Johnson counter to provide the feedback signal to the                      
                     second input of the phase lock loop circuit having a frequency corresponding to                   
                     the frequency of the output signal of the phase lock loop circuit divided by 2N, the              
                     Johnson counter comprising N JK flip-flops including an input JK flip-flop, an                    
                     output JK flip-flop, and a plurality of middle JK flip-flops, each JK flip-flop having            
                     a J input, a K input, the clock input, a Q output, and a complemented Q output,                   
                     each middle JK flip-flop and the output JK flip-flop having its J input coupled to                
                     the Q output of a preceding JK flip-flop and its K input coupled to the                           
                     complemented Q output of the preceding JK flip-flop, the J input of the input JK                  
                     flip-flop being coupled to the complemented Q output of the output JK flip-flop,                  
                     the K input of the input JK flip-flop being coupled to the Q output of the output JK              
                     flip-flop; and                                                                                    
                            coupling outputs of the JK flip-flops of the Johnson counter for use as                    
                     phase shifted clock outputs.                                                                      





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