Appeal No. 2006-2412 Page 2
Application No. 09/892,424
Claim 1 is illustrative of the claimed invention, and it reads as follows:
1. A computer system comprising:
at least one processor;
a memory coupled to the at least one processor;
a performance data collection mechanism residing in the memory and executed by
the at least one processor, the performance data collection mechanism collecting
performance data for the computer system;
a performance data transmission mechanism residing in the memory and executed
by the at least one processor, the performance data transmission mechanism, when
enabled, transmitting at least a portion of the performance data to another computer
system coupled to the computer system via a network; and
a performance data access mechanism residing in the memory and executed by
the at least one processor, the performance data access mechanism allowing access to the
performance data by a user of the computer system only if the performance data
transmission mechanism is enabled.
The reference relied on by the examiner is:
Duimovich et al. (Duimovich) 2002/0052947 May 2, 2002
(filed Apr. 3, 2001)
Claims 1 through 22 stand rejected under 35 U.S.C. § 102(e) as being anticipated
by Duimovich.
Reference is made to the briefs and the answer for the respective positions of the
appellants and the examiner.
OPINION
We have carefully considered the entire record before us, and we will reverse the
anticipation rejection of claims 1 through 22.
Anticipation is established only when a single prior art reference discloses,
expressly or under the principles of inherency, each and every element of a claimed
invention as well as disclosing structure which is capable of performing the recited
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