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Ex parte LOO et al. - Page 6
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Board of Patent Appeals and Interferences > 1997 > Ex parte LOO et al. - Page 6
Appeal No. 95-4714
Application No. 08/046,476
has been checked (Spec. at 29, lines 20-22).
During a flush operation, all thirty-two cache blocks in the
cache data array are addressed in sequence using the virtual
address bits A(8:4) generated by 5-bit incrementer 50 (Spec. at
29, lines 10-15). As is apparent from Figure 11, an addressed
cache block is flushed (i.e., a Flush Match signal is generated
by OR gate 58 of Fig. 11) only if the Context Flush, Page Flush,
or Segment Flush signal stored in one of flip-flops 49 is applied
to one input of an AND gate 55 at the same time that a Context
Match, Page Match, or Segment Match signal is applied to the
other input of that AND gate. These Match signals are produced
by the circuitry shown in Figure 12 (Spec. at 28, lines 18-20),
which compares the virtual address A(27:4) of the addressed cache
block (including the cache block address and the associated
address information in the cache tag array) with the virtual
addresses to be flushed, compares the context identification
bits CX(2:0) of the addressed cache block with the context
identification bits of the virtual addresses to be flushed, and
examines the Valid (V), Modified (M), and Protection (P) bits
stored in the cache tag array for the addressed block (Spec. at
15-17).
The foregoing elements clearly perform the functions
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Last modified: November 3, 2007
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