Appeal No. 1999-0528
Application 08/472,770
Representative claim 19 is reproduced below:
19. A semiconductor memory device comprising:
a main memory divided into a plurality of blocks in the unit of a plurality of columns,
including
a plurality of memory cells for storing information, arranged in a plurality of rows and
a plurality of columns, each being formed of one transistor element and one capacitor
element,
a plurality of word lines disposed in a plurality of rows, each having a plurality of
memory cells arranged in a corresponding row connected thereto, and
a plurality of parallel-disposed bit line pairs, arranged in a plurality of columns, each
having a plurality of memory cells arranged in a corresponding column connected thereto,
and
a plurality of sense amplifiers arranged in a plurality of columns, and connected to a
bit line pair of a corresponding column, for sensing and amplifying the potential difference
appearing on said bit line pair of said corresponding column,
a date output line for providing data,
a plurality of circuits, each being provided corresponding to each block of said main
memory, for providing or not providing information read out from a corresponding block of
said main memory to said data output line, said plurality of circuits including a cache
memory for storing the information read out from said main memory, said cache memory
being arranged in a plurality of rows corresponding to said plurality of bit line pairs, and
a wiring arranged in a region adjacent said plurality of circuits, and connected to the
circuits of said plurality of circuits,
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