Appeal No. 1999-0528
Application 08/472,770
figure. Note the depiction in the figure with respect to the individual interconnect-ability of
the lines from the bit decoder through the isolators to the master register 22. In this light,
note also the teachings at column 3, lines 30 through line 35. Within these lines there is
stated the “master/slave row buffer 15 comprises a master register 22 and a slave register
23 each N bits wide corresponding to the width of the storage array and each composed
of master/slave latches.” (Emphasis added). As indicated earlier at lines 30 through 31
and at column 4, lines 3 and 4 the master register receives an entire row of data from the
storage array comprising the DRAM above it in figure 1. Thus, we conclude that the
latches comprising the master register 22 and slave register 23 correspond to the claimed
storage elements of representative claim 19 on appeal and are aligned directly with
respect to the respective bit/column lines of the DRAM array above it as the examiner
asserts and is claimed.
The teachings in Matick make clear that the bandwidth is so wide, that is, the
bussing between the master and slave registers in the DRAM array itself is so wide, that
there is no interconnectability problem between them. Thus, the discussion at the middle
of page 11 of the brief pertains only to the architecture with respect to the relationship of
the master and slave registers but not between the DRAM array itself and the cache as a
whole as represented by buffer 15. The argument by appellants that the artisan would not
appreciate the pitch of the bit lines being representative in this reference in the detail
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