Appeal No. 1999-0528
Application 08/472,770
required by the claim is based on speculation and traversed by the noted teachings above
that we have outlined from the reference itself.
We are unpersuaded of appellants' second argument at page 12 of the brief that
the slave register 23 and the master register 22 comprise a single buffer. Appellants'
urging the Matick's real buffer does not comprise an arrangement of a plurality of rows is
misplaced because the single buffer comprises two separate registers which can be
clearly considered to be separate row registers that receive data dumped successively by
row from the DRAM storage array into the master register first and from the master
register into the slave register. In any event, the examiner has asserted and appellants
have noted at page 9 of the brief that column 7, lines 49 through 53 of Matick indicate that
there maybe “more than one row buffer per chip.”
Additionally, we note that figure 2 shows that the cache memory comprising the
buffer 15, which in turn comprises the master and slave registers 22 and 23, has the
capacity of 512 bits which is double the arrangement of a single row of the 256 K bit
DRAM array itself. Thus, each of the respective master and slave registers comprise 256
bits or one row of the DRAM array itself. This also argues for a proper consideration of the
reference indicating an alignment of the storage positions in the master and slave
registers comprising the cache with those particular positions correspondingly located in
the DRAM array itself.
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