Appeal No. 1999-0528
Application 08/472,770
does not in effect store an entire row of the DRAM array itself. The abstract clearly states
that “[e]ach static data buffer is connected to the memory array to receive and store a row
of data from any addressed row of the array.” Even in accordance with the prior art
discussed at column 1, lines 24 through 27, Ward states that “[a]n entire row of the two-
dimensional array, dictaterd [sic] by high-order address bits, is loaded into the row buffer
on the row address strobe (RAS) signal.” Note also the teachings at column 2, lines 15
through 24. Finally, we note column 3, lines 50 through 54 state that an “advantage of the
system over conventional cache systems is that a full row of data from adjacent storage
elements, not just a single bit per memory chip, can be addressed and held in the buffers
which serve as cache memory.”
Thus, we are in agreement with the examiner's view that the alignment taught to the
artisan within 35 U.S.C. § 103 from this reference is the same alignment broadly recited in
the claims on appeal. We observe that appellants' admitted prior art figure 1
has more details regarding the memory array itself as comprising word lines and bit line
pairs. The noted teachings in Ward taken alone, or further in view of what is well-known in
the art as represented by appellants' admitted prior art figure 1 for the details of the
construction of the DRAM and memory array itself, would have indicated to the artisan the
alignment of the type recited in the representative independent claim 19 on appeal.
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