Appeal No. 1999-0528
Application 08/472,770
As to the rejection involving Matick under 35 U.S.C. § 102, it appears that
appellants' principal argument is that this reference does not expressly describe bit lines of
the storage array or the arrangement of the latches in the row buffer 15. Appellants
disagree with the examiner's view that each latch in the buffer memory 15 must be aligned
with the bit line pairs in the same manner in order to receive the data from the bit lines from
the DRAM storage array. We are unpersuaded of appellants' arguments.
The abstract of Matick indicates twice that the disclosed invention has a large
bandwidth between the main memory and the cache memory stated to be “the usual on-
chip interconnecting lines which avoids pin input/output problems.” This bandwidth
architecture is described in detail beginning at column 4, line 15. The background of the
invention portion at column 1 of Matick indicates that a deficiency of the prior art on-chip
cache memories of the prior art at that time was that they had a very limited
bandwidth capability, which is essentially a limited bus width between the main memory
and the cache memory.
The showing in figure 1 of Matick indicates to us that the latches described in the
specification to comprise the master register and slave registers respectively both
comprising the buffer 15 to be directly interconnected respectively to each bit decoder for
each bit line of the storage array comprising the DRAM above the cache memory in this
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