Appeal No. 95-1851
Application 07/902,186
address where said new value of display data is stored
within said frame buffer memory means in response to
said frame buffer write detect means;
providing address translate logic means for generating
an appropriate start address for updating said display
means based on said affected address within said frame
buffer memory means where said new value of display
data was stored; and
providing blocking means for selectively blocking
memory accesses to said frame buffer memory means which
fall outside the range of applicable display data for
said display means.
Opinion
On pages 2-3 of the answer, the examiner specifically
describes the teachings of Belch. Notably absent from that
description is any discussion of displaying full resolution VGA
display data on a "lower" resolution display device. Of course,
there is no discussion about any address translation to produce a
startng address for updating the "lower" resolution display
device. The examiner has pointed to nothing in Belch which
discusses the use of a "lower" resolution display device.
Nonetheless, the examiner concludes on page 3 of the answer:
"It would have been obvious to have a lower resolution display in
Belch's circuit for displaying high resolution data since Belch's
display can present only a part of the data stored in a
memory(IS) (see column 1, lines 11-13)." The examiner further
states on the same page: "The use of a VGA controller as a
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Last modified: November 3, 2007