Ex parte BATES et al. - Page 2




          Appeal No. 95-2219                                                          
          Application 08/041,922                                                      


               The invention relates to processing of iterative tasks in              
          data processors.                                                            
               The independent claims 1 and 15 are reproduced as follows:             
               1.  A processor comprising:                                            
               means for storing a plurality of values at addressable                 
          storage locations;                                                          
               means for storing a processor condition code; and                      
               logic for decoding instructions from a sequence of stored              
          instructions, said instructions including a specific instruction            
          defining an operation between a first value at a first address              
          specified by said instruction, and a second value at a second               
          addressable storage location, the second addressable location               
          determined from a second address specified in said instruction              
          and the state of said processor condition code.                             
               15.   Processing apparatus comprising:                                 
               means for fetching instructions from storage for decoding              
          and execution, said instructions including a specific instruction           
          defining an operation between a first operand comprising a first            
          addressable value and a second operand comprising either a second           
          addressable value or a third addressable value depending on a               
          processor condition code; and                                               
               means for decoding the instructions fetched from storage by            
          said fetching means, said decoding means decoding said specific             
          instruction by selecting an address of one of said second and               
          third addressable values as said second operand based on said               
          condition code.                                                             
               The Examiner relies on the following reference:                        
          Brown et al. (Brown)          4,677,573           June 30, 1987             
               Claims 1 through 20 stand rejected under 35 U.S.C.  103 as            
          being unpatentable over Brown.                                              

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