Ex parte TSUTSUMI - Page 2




          Appeal No. 95-4183                                                          
          Application 07/945,714                                                      

                    The invention pertains to a video image display device            
          as described by claim 14 reproduced as follows:                             
                    14. A video image display device comprising:                      
                    an address selector circuit responsive to a line                  
          selection signal for determining a vertical position on a display           
          screen and a column selection signal for determining a horizontal           
          position on the display screen to produce a first address signal            
          and a second address signal;                                                
                    a display data random access memory for storing all               
          character codes to be displayed and reading and outputting one of           
          said character codes stored in an address indicated by said first           
          address signal;                                                             
                    a single chip IC character generator comprising a read            
          only pattern memory for storing a plurality of character patterns           
          each composed of a plurality [sic, of] pattern lines each                   
          composed of a bit pattern, and an address determination circuit             
          and a selector circuit operable, in response to said character              
          code and said second address signal, to select one of said                  
          character patterns corresponding to said character code and                 
          output a bit pattern signal of one of said pattern lines                    
          corresponding to said second address signal; and                            
                    a serial converter circuit responsive to a fringe                 
          request signal from a microcomputer to generate a bit pattern of            
          fringe for said bit pattern of said character pattern and output            
          signals of said fringe bit pattern and said bit pattern of said             
          character pattern dot by dot every clock having a period                    
          corresponding to a horizontal scan period of respective display             
          dots on the display screen,                                                 
                    wherein said read only pattern memory stores all of               
          said pattern lines of each of said character patterns, and                  
          selects, in response to said character code, one of said                    
          character patterns and outputs said bit pattern of said selected            
          character pattern corresponding to said second address signal               
          when a value of said second address signal indicates any of said            
          pattern lines;                                                              



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