Appeal No. 95-4788
Application 07/996,393
sequence corresponds to data, data complement, data, data complement, etc., with the gate pulses
synchronized to the intervals of the data voltage for transferring charge to the cell capacitance 40
and the data complement pulses driving the column electrodes when there are no gate pulses
active, thereby compensating for the effect of crosstalk via capacitive coupling by the cell
capacitances 42 and 44 (column 3, line 66 to column 4, lines 1-9). That is, the data signal is
applied to one of the data lines when the gating signal is applied and the crosstalk compensation
signal is applied when the gating signal is not applied. A variation is to trade a longer duration
data signal time for a shorter duration compensation signal with increased amplitude, e.g., the gate
signal being ON for a time 0.8T/N during which period from 0 to 0.8T/N the data signal is applied
and the gate signal being off during the time 0.8T/N to T/N during which period the crosstalk
compensation of amplitude 2(V -V ) is applied.
M i
Claims 3-5 stand rejected under 35 U.S.C. § 103 as being unpatentable over the admitted
prior art and Howard. The examiner finds that Howard teaches a circuit which produces two
voltage levels (e.g., V and V -V shown in figure 5) at the output of the analog toggle 48. Thei M i
examiner states (Examiner's Answer, page 5):
It is well known in the art of solid state imaging that for sweep and transfer clock pulses
generated during the vertical blanking period, the power dissipation caused by the high
repetition rates that are required can cause the generation of undesirable heat contributing
to an increase in unwanted charges due to thermal noise. It is also standard practice in the
design of solid state imagers, as seen in the admitted prior art device, to provide a means
for varying the amplitude of clock pulse voltages. Thus, it would have been obvious to
one of ordinary skill in the art at the time the invention was made to control the variations
in the prior art clock pulse voltages in accordance with the dual-voltage control means
disclosed in Howard et al. in order to provide different clock voltages for the respective
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