Appeal No. 96-0506
Application 07/856,001
This is a decision on appeal under 35 U.S.C. § 134 from the final rejection of claims 1-10, all
the claims pending in the application. In the Examiner's Answer, the examiner maintained the
provisional obviousness-type double patenting rejection of claims 1-10 over claims 1-4 of Application
07/856,002 because that application had not yet been abandoned. Since the status of 07/856,002 is
now abandoned, it is presumed that the double patenting rejection is now moot. Accordingly, only
claims 1-6 stand finally rejected.
The disclosed invention is directed to a method for reading and writing a two-dimensional
code having parity protection along multiple axes.
Claim 1 is reproduced below.
1. In a method for writing and reading a parity protected binary message of predetermined
symbol size into and from, respectively, a two dimensional code; the improvement comprising
the steps of
padding said message with a predetermined set of constant bit values to provide a first array
of bits that is symbol aligned for certain scan patterns, where the only variables are message
bits;
reading out said first array in accordance with a predetermined one of said scan patterns to
provide a first set of symbols that are a disjoint cover of said array;
computing at least one symbol oriented error correction code on said first array of bits to
produce parity symbols for protecting said message against an anticipated burst error pattern;
encoding said message and a selected number of said parity symbols in said code;
decoding said code for recovering decode values for said message and for said parity symbols;
separating the decode values for said message from the decode values for said parity symbols;
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